By Anton Bakker (auth.), J. H. Huijsing, Michiel Steyaert, Arthur van Roermund (eds.)
Analog Circuit Design includes the contribution of 18 specialists from the thirteenth overseas Workshop on Advances in Analog Circuit layout. it truly is quantity thirteen within the winning sequence of Analog Circuit Design.
It presents 18 first-class overviews of analog circuit layout in: Sensor and Actuator Interfaces, built-in High-Voltage Electronics and gear administration, and Low-Power and High-Resolution ADC’s.
Analog Circuit Design is a necessary reference resource for analog circuits designers and researchers wishing to maintain abreast with the most recent advancements within the box. the educational assurance additionally makes it appropriate to be used in a sophisticated layout course.
Read or Download Analog Circuit Design: Sensor and Actuator Interface Electronics, Integrated High-Voltage Electronics and Power Management, Low-Power and High-Resolution ADC’s PDF
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Additional resources for Analog Circuit Design: Sensor and Actuator Interface Electronics, Integrated High-Voltage Electronics and Power Management, Low-Power and High-Resolution ADC’s
If CC2 remained connected between gml and gmS during phase 1, however, it would disturb the autozeroing of gml by gm2 whenever V 0 changed. To prevent this disturbance, CC2 is disconnected from gml and connected to a voltage VI during phase 1; VI should have the same voltage as the inverting output of gml. That way, CC2 continues to be charged by changes in Va, minimizing output glitches when it is re-connected to gml at the beginning of phase 2. 2 Intermodulation Distortion One may suspect that switching between two gain stages during phase 1 and three gain stages during phase 2 might lead to severe distortion.
Gml to Unfortunately, the differential input of gm2 will change slightly during phase 2. There are two reasons. 1. Charge injection from the switches across gm2. Charge is injected from the MOS switches onto capacitors Cl and C 2 when the switches are opened [2, 3]. This causes changes in the voltages stored at Cl and C 2. This error can be minimized by making CI and C 2 large and the MOS switches small. Making gm2 differential (as illustrated in Figure 3) helps because the charge injection is similar at CI and C 2 , allowing the most of the charge injection error to be cancelled by the common-mode rejection of gm2 (assuming the voltage across CI is similar to the voltage across C 2).
MOS switches will therefore draw current from Cl and C 2, causing the stored voltage to change (especially at high temperatures). Again, making gm2 differential helps to reduce this error because the discharge of Cl and C 2 will be similar (assuming Cl and C 2 are matched and the MOS switches are matched). By comparison, a single-ended implementation of gm2 will be far more sensitive to MOS switch leakage. If the total error introduced at the input of gm2 is V t" the input-referred offset of the autozeroed amplifier will change by: (9) Adding this error term to equation (8) gives the input-referred offset during phase 2 as: (10) Re-writing equation (10) will give a clearer picture of the trade-off between gml and gm2: (11) is the dominant contributor to V OSAZ if gml/gm2 is too large.
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