By M. Gasteier, S. Liao, X. Song on the crossing distribution problem, J.-Y. Jou on two-level logic minimization for low power, F. Vahid on procedure cloning, Q. Wang, G. Yeap on power reduction and power delay trade-offs, others M. Glesner

Significant reports through top overseas computing device scientists.

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Extra resources for ACM Transactions on Design Automation of Electronic Systems (January)

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Assume at some point we are about to schedule a path that contains an operation which has some already scheduled successor(s). If the earliest possible start for the predecessor operation is later than the earliest scheduled successor, then we insert extra control steps right before the earliest scheduled successor and push all operations starting at or later than this step by the delay of the predecessor operation. If the earliest possible start of the predecessor operation is earlier or at the same time as the earliest scheduled successor operations (probably the predecessor operation has large delay, such that its result is not ready for the earliest scheduled successor although it can start before the earliest scheduled successor), then we need to determine the number of extra control steps to be inserted as follows.

Fig. 3. (a) Bipartite graph representing the matching between operations in a path and control steps. (b) A noncrossing bipartite matching between operations and control steps. Op6 and Op9 . The earliest possible matching for the parent operation is to control step 2. Therefore, there cannot be any edge between the child operation, Op9 , and any control step earlier or equal to control step 2. Also, as operations from extracted paths are scheduled, their start and finish times restrict the intervals of control steps within which their predecessors and successors need to be scheduled.

While internal representations in different compilers take different forms and names, essentially they capture two basic pieces of information about an application: control flow and data dependency. A high-level synthesis stage follows the compiler stage and takes the optimized IR as input and generates the register transfer level (RTL) description of the design. Back-end tools perform logic synthesis and physical synthesis on this RTL description and create the bit-stream data to program the target system.

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